Traffic Light Controller Using VHDL

Design of an FPGA Based Intelligence Traffic Light Controller with VHDL 

module traffic_controler(north,west,rst,clk);
output north,west;
input rst,clk;
parameter red=2'd0,green=2'd1;
parameter s0=2'b00,s1=2'b01,s2=2'b10,s3=2'b11;
reg [1:0] north;
reg [1:0] west;
reg[1:0] p_state;
reg[1:0] n_state;
reg[5:0] count;
reg [24:0] cnt;
reg clk1;
always @(posedge clk or posedge rst)
      begin
      if(rst)
            begin
            cnt<=0;
            clk1<=1'b1;
            end
      else
            if(cnt==25000000)
            begin
            cnt<=0;
            clk1<=~clk1;
            end
            else
            begin
      cnt<=cnt+1;
      clk1<=clk1;
end
end
always @(posedge clk or posedge rst) //Present State Block
begin
if(rst)
begin
p_state<=s0;
end
else
begin
p_state<=n_state;
end
end
 always @(posedge clk or posedge rst) //Next State Block
 begin
 if (rst)
 begin
 n_state<=s0;
 count<=0;
 end
 else
 begin
             case(p_state)
       s0:
begin
       if(count==2)
       begin
       n_state<=s1;
       count<=0;
       end
       else
       begin
   count<=count+1;
      n_state<=n_state;
      end
      end
       s1:
       begin
       if (count==50)
       begin
       n_state<=s2;
       count<=0;
       end
       else
       begin
   count<=count+1;
      n_state<=n_state;
        end
        end
        s2:
        begin
        if (count==2)
     begin
       n_state<=s3;
       count<=0;
       end
       else
       begin
   count<=count+1;
      n_state<=n_state;
       end
       end
       s3:
        begin
        if (count==30)
     begin
       n_state<=s0;
       count<=0;
       end
       else
       begin
   count<=count+1;
      n_state<=n_state;
       end
       end
       endcase
       end
       end
        always @(posedge clk or posedge rst)  //Output  Block
begin
  if(rst)
  begin
  north<=0;
  west<=0;
  end
  else
  begin
  case(p_state)
  s0:
   begin
  north<=red;
  west<=red;
  end
  s1:
  begin
  north<=green;
  west<=red;
  end
  s2:
  begin
  north<=red;
  west<=red;
  end
  s3:
  begin
  north<=red;
  west<=green;
  end
  endcase
  end
  end
endmodule 

A complete Test Bench For this 

module test;

      // Inputs

      reg peak;

      reg clk;

      reg rst;

      reg sen1;

      reg sen2;

      // Outputs

      wire [2:0] t1;

      wire [2:0] t2;

      wire [2:0] t3;

      wire [2:0] t4;

      wire [2:0] t5;

      wire [2:0] t6;

      // Instantiate the Unit Under Test (UUT)

      trafficcontroller1 uut (

            .peak(peak),

            .clk(clk),

            .rst(rst),

            .sen1(sen1),

            .sen2(sen2),

            .t1(t1),

            .t2(t2),

            .t3(t3),

            .t4(t4),

            .t5(t5),

            .t6(t6)

      );

      initial begin

            // Initialize Inputs

            clk = 0;
         forever  #10 clk = ~clk;

            peak = 0;
      rst = 0;

            sen1 = 0;

            sen2 = 0;

# 10 

         peak = 0;

            rst = 0;

            sen1 = 1;

            sen2 = 1;

# 10 

      peak = 1;

            rst = 0;

            sen1 = 1;

            sen2 = 0;

# 10 

      peak = 1;

            rst = 0;

            sen1 = 0;

            sen2 = 1;

#10  

      peak = 1;
      rst = 0;

            sen1 = 1;

            sen2 = 1;

# 10 

         peak = 0;

            rst = 0;

            sen1 = 0;

            sen2 = 0;        

            // Wait 100 ns for global reset to finish

            #100;

       

            // Add stimulus here

      end

     

endmodule