output [2:0] out;
reg [2:0] out,count,n_l_wait,x_c_wait;
input rst,clk;
input [2:0] req_floor;
reg [2:0]nxt_state,pst_state;
parameter reset=3'd0,s1=3'd1,s2=3'd2,s3=3'd3,s4=3'd4;
//Present State
always @(posedge clk)
begin
if(rst)
begin
pst_state<=reset;
end
else
begin
pst_state<=nxt_state;
end
end
//Next State
always @ (posedge clk)
begin
if(rst)
begin
nxt_state<=reset;
end
else
begin
case(pst_state)
reset:
if(req_floor)
begin
n_l_wait<=3'd0;
nxt_state<=s1;
end
else
begin
nxt_state<=reset;
end
s1:
if(n_l_wait==3'b101)
begin
count<=3'd0;
nxt_state<=s2;
end
else
begin
n_l_wait<=n_l_wait+1;
end
s2:
if(count==req_floor)
begin
x_c_wait<=3'd0;
nxt_state<=s3;
end
else
begin
count<=count+1;
end
s3:
if(x_c_wait==3'd5)
begin
nxt_state<=s4;
end
else
begin
x_c_wait<=x_c_wait+1;
end
s4:
if(rst)
begin
nxt_state<=reset;
end
default:
nxt_state<=reset;
endcase
end
end
//Output State
always @ (posedge clk)
begin
if(rst)
begin
out<=3'd0;
end
else
begin
case(pst_state)
reset:
if(req_floor>3'd0)
begin
out<=req_floor;
end
else
begin
out<=out;
end
s1:
if(n_l_wait==3'd5)
begin
out<=3'd0;
end
else
begin
out<=out;
end
s2:
if(count==req_floor)
begin
out<=count;
end
else
begin
out<=count;
end
s3:
if(x_c_wait==3'd5)
begin
out<=out;
end
s4:
if(rst)
begin
out<=3'd0;
end
default:
out<=3'd0;
endcase
end
end
endmodule
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