Seven Segment Display On FPGA using VHDL

module sevenseg

(
  an1,
    an2,
    an3,
     an4,
     seg,
        rst,
     clk
    );
    output an1;
    output an2;
    output an3;
    output an4;
    output [6:0] seg;
    input clk,rst;
   
    reg an1;
    reg an2;
    reg an3;
    reg an4;
    reg [6:0] seg ;
    reg [6:0] seg1 ;
        reg [6:0] seg2 ;
        reg [26:0]  count1; 
        reg [30:0]  count2;
     reg [3:0]   count7;     
         reg [3:0]   count15;
        reg [1:0]  countAN;
        reg     clk1ms;  
     reg     clk1s;        
       
        always @(posedge clk or posedge rst)
        if(rst)
        begin
        count1<=0;
        clk1ms<=0;
        end
        else
        if (count1==100000) //200000
        begin
        clk1ms <= ~clk1ms;
        count1 <= 0;
        end
        else
        begin
        clk1ms <= clk1ms;
        count1 <= count1 + 1;
        end
       
        always @(posedge clk or posedge rst)
         if(rst)
        begin
        clk1s <= 0;
        count2 <= 0;
        end
        else
        if (count2==25000000)
        begin
        clk1s <= ~clk1s;
        count2 <= 0;
        end
        else
        begin
        clk1s <= clk1s;
        count2 <= count2 + 1;
        end                 
                         
        always @(posedge clk1ms or posedge rst)
        if(rst)
        begin
        an1<=0;
        an2<=0;
        an3<=0;
        an4<=0;
        countAN <= 0;
        seg <= 7'b0000000;
        end
        else
        case (countAN)
        0: begin
           an1<=0;
           an2<=1;
           an3<=1;
           an4<=1;
           countAN <= countAN  + 1;
          seg <= seg1;
           end
        1: begin
           an1<=1;
           an2<=0;
           an3<=1;
           an4<=1;
           countAN <= countAN  + 1;
           seg <= seg2;
           end
        2: begin
           an1<=1;
           an2<=1;
           an3<=0;
           an4<=1;
           countAN <= countAN  + 1;
          seg <= 7'b0000001;
           end
        3: begin
           an1<=1;
           an2<=1;
           an3<=1;
           an4<=0;
           countAN <= 0;
          seg <= 7'b0000001;
           end
       
       
       
        endcase
       
              always @(posedge clk1s or posedge rst)  // is we run this at clk1ms it will always display 1234
                    if(rst)
                    begin
                    count7<=0;
                    count15<=0;
                    end
                    else
             
              if(count7==9)
              begin
              count7<=0;             
              if(count15==9)
              count15<=0;
              else
              count15<=count15+1;
              end
              else
              begin
              count7 <= count7 + 1;
              count15<=count15;
              end
             
             
      always @(count7)
     
case (count7)          //abcdefg
           4'b0000: seg1=7'b 0000001;
       4'b0001: seg1=7'b 1001111;
       4'b0010: seg1=7'b 0010010;
       4'b0011: seg1=7'b 0000110;
       4'b0100: seg1=7'b 1001100;
       4'b0101: seg1=7'b 0100100;
       4'b0110: seg1=7'b 0100000;
       4'b0111: seg1=7'b 0001111;
       4'b1000: seg1=7'b 0000000;
       4'b1001: seg1=7'b 0000100;
endcase    
always @(count15)
     
case (count15)
           4'b0000: seg2=7'b 0000001;
       4'b0001: seg2=7'b 1001111;
       4'b0010: seg2=7'b 0010010;
       4'b0011: seg2=7'b 0000110;
       4'b0100: seg2=7'b 1001100;
       4'b0101: seg2=7'b 0100100;
       4'b0110: seg2=7'b 0100000;
       4'b0111: seg2=7'b 0001111;
       4'b1000: seg2=7'b 0000000;
       4'b1001: seg2=7'b 0000100;
endcase    
endmodule